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HUSTIR > College of Engineering > Department of Electrical Engineering & Graduate Institute > Monograph > Item 310993100/3298

Please use this identifier to cite or link to this item: http://ir.hust.edu.tw/dspace/handle/310993100/3298

Title:	5T靜態隨機存取記憶體(II)
Authors:	許景程蔡仲軒
Contributors:	電機工程系
Keywords:	待機啟動電路寫入模式讀取模式待機模式漏電流
Date:	2012-11-12
Issue Date:	2013-07-23T06:12:54Z
Abstract:	本專題提出一種具高效能之5T SRAM，有效防止寫入邏輯 1 困難之問題，於讀取模式時，可有效提高讀取速度，而於待機模式時，則可有效降低漏電流。再者，藉由待機啟動電路的設計，可有效促使5T SRAM 快速進入待機模式，並因而大幅提高靜態隨機存取記憶體之待機效能。
Appears in Collections:	[Department of Electrical Engineering & Graduate Institute] Monograph

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