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HUSTIR > College of Engineering > Department of Electrical Engineering & Graduate Institute > Journal > Item 310993100/1259

Please use this identifier to cite or link to this item: http://ir.hust.edu.tw/dspace/handle/310993100/1259

Title:	General and efficient timing models for CMOS AND-OR-INVERTER and OR-AND-INVERTER gates
Authors:	C. Y. Wu;M. C. Shiau
Date:	1990-09
Issue Date:	2009-02-03T06:47:55Z
Relation:	IEEE Trans. Computer-Aided-Design, pp. 1002-1009
Appears in Collections:	[Department of Electrical Engineering & Graduate Institute] Journal

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